1. Field of the Invention
The present invention relates to a simulation apparatus for simulating a process of manufacturing a semiconductor device and, more particularly, to a semiconductor manufacturing process simulation apparatus using a diffusion model in which an influence of a dislocation loop generated within a crystalline substrate during an ion implantation process is considered with respect to diffusion in a heat treatment process subsequent to the ion implantation process.
2. Description of the Related Art
In the recent development work of semiconductor devices, a semiconductor manufacturing process simulation apparatus plays an important role. Commercially available process simulation apparatuses have become popular, and are used by persons working on a semiconductor device developments
However, simulation models used in the commercially available process simulation apparatuses are incomplete with respect to a physical aspect, and there are many cases in which matching of parameters for simulation is needed for each process performed in a manufacturing process of a semiconductor device.
Particularly, a temperature of a heat treatment process has been decreased in recent years. A crystal defect in a silicon wafer did not have an influence in a conventional manufacturing process using a high temperature for a heat treatment process. However, in the heat treatment process using a low temperature, it is considered that a crystal defect of a silicon wafer influences diffusion of impurities during a heat treatment process.
A crystal dislocation loop related to the present invention influences diffusion of impurities in a heat treatment process using a low temperature. However, the influence of such a crystal dislocation loop is not considered in the commercially available semiconductor manufacturing process simulation apparatus. Additionally, there is no method announced in publicly known literature such as a treatise or a patent publication that indicates practical use of a model of a crystal dislocation loop for a two-dimensional semiconductor manufacturing process simulation apparatus.
It should be noted that a series of treatises have been published by Mark E. Law and his group which relate to a semiconductor manufacturing process simulation apparatus using a impurity diffusion model considering dislocation loops generated in a crystal structure due to ion implantation.
An example of the recent publication is "J.Electrochem. Soc., Vol. 141, 759 (1994)" by H. Park, K. S. Jones and M. E. Law. In the series of treatises, influence of dislocation loops in an impurity diffusion model is described. However, no consideration was made with respect to a method regarding how to define and input location of a dislocation loop and to which process influence or contribution of a dislocation loop should be considered with respect to processes subsequent to an ion implantation process. Such information is needed for constructing the process simulation apparatus according to the present invention.
That is, according to the series of publications related to a model handling the crystal dislocation loop, the following two issues must be considered when the model is used for a two-dimensional semiconductor process simulation apparatus.
(1) How to define location of a dislocation loop.
(2) To which process the influence or contribution of a dislocation loop regarding diffusion of impurities should be considered with respect to processes subsequent to an ion implantation process.
Additionally, the issue regarding the method for defining location of a dislocation loop mentioned in the above item (1) includes the following two secondary issues.
(a) What assumption can be used when a function representing an average pressure field is calculated based on a function which provides contribution of a single crystal dislocation loop. The average pressure field is generated by dislocation loops distributed in a layer in which the dislocation loop is located.
(b) How to input information regarding location of the dislocation loop to a semiconductor manufacturing process simulation apparatus using a two-dimensional model.
With respect to the above-mentioned issue (a), the published literatures (for example, "H. Park, K. S. Jones and M. E. Law, J., Electrochem. Soc., Vol. 141, 759 (1994)") teach a method for calculating the average pressure field, which is a sum of dislocation loops located in a layer, based on the pressure generated by each dislocation loop. The assumptions used for the calculation are as follows.
the layer 12 (hereinafter referred to as a dislocation loop layer) in which dislocation loops are formed is a flat plane (refer to FIG. 1) PA1 the dislocation loops 16 distributed in the dislocation loop layer 12 is perpendicular to the plane representing the layer and they are perpendicular to each other (refer to FIG. 2) PA1 six (6) most adjacent dislocation loops are taken into consideration (refer to FIG. 3) PA1 an ion implantation process simulating part which simulates an ion implantation process; PA1 a model generating part which generates a diffusion model in which contribution of dislocation loops is considered, the dislocation loops being formed in the substrate during the ion implantation process; and PA1 a heat treatment process simulating part which simulates a heat treatment process subsequent to the ion implantation process, the diffusion model generated by the model generating part being used for simulating diffusion of impurities in the substrate during the heat treatment process, PA1 wherein a pressure field generated by the dislocation loops in the substrate is defined in the diffusion model by a function of a distance from a layer in which the dislocation loops are formed. PA1 wherein the model generating part comprises: PA1 computer-readable program code means for simulating an ion implantation process; PA1 computer-readable program code means for generating a diffusion model in which contribution of a dislocation loop is considered, the dislocation loop being formed in the substrate during the ion implantation process; PA1 computer-readable program code means for defining a pressure field generated by the dislocation loop in the substrate by a function of a distance from the dislocation loop; and PA1 computer-readable program code means for simulating a heat treatment process subsequent to the ion implantation process, the diffusion model being used for simulating diffusion of impurities in the substrate in the heat treatment process. PA1 first program code means for simulating an ion implantation process; PA1 second program code means for generating a diffusion model in which contribution of a dislocation loop is considered, the dislocation loop being formed in the substrate during the ion implantation process; PA1 third program code means for defining a pressure field generated by the dislocation loop in the substrate by a function of a distance from the dislocation loop; and PA1 fourth program code means for simulating a heat treatment process subsequent to the ion implantation process, the diffusion model being used for simulating diffusion of impurities in the substrate in the heat treatment process.
Based on the above-mentioned assumptions, the function representing the average pressure field due to the dislocation loops can use a distance from the dislocation loop layer as an argument. Due to the assumption used when the average pressure field is calculated, the dislocation loop layer, in which the dislocation loops are formed, must be a flat plane. However, in a practical manufacturing process of a MOS device, a gate area is used as a mask in the ion implantation process for forming a source area and a drain area. Thus, the dislocation loop layer is not always a flat plane as indicated by a solid line 203 in a two-dimensional cross section shown in FIG. 5.
Accordingly, in order to use the model of the crystal dislocation loop in a semiconductor manufacturing process simulation apparatus using a two-dimensinal model (hereinafter referred to as a two-dimensional semiconductor manufacturing process simulation apparatus), the average pressure field must be defined when the dislocation loop layer is not a flat plane. However, none of the publications teaches such a definition.
Additionally, with respect to the issue mentioned in the item (b), it is considered that the dislocation loop layer is formed in a boundary between an amorphous area and a crystal area formed in a silicon wafer in an ion implantation process. However, there is no publication which suggests a method for representing a configuration of the dislocation loop layer and a method for designating a position of the dislocation loop layer which is convenient for a user of the semiconductor manufacturing process simulation apparatus.
Additionally, the crystal dislocation loops formed in a silicon wafer in an ion implantation process are grown or reduced by a heat treatment subsequent to the ion implantation process, and the dislocation loops finally disappear. The model described in the publications (for example, "H. Park, K. S. Jones and M. E. Law, J. Electrochem. Soc., Vol. 141, 759 (1994)") can represent a process of growth or reduction in a relatively earlier stage of a heat treatment subsequent to an ion implantation process. However, a process of causing the dislocation loops to disappear over a relatively long period is not represented.
Accordingly, if a plurality of heat treatment processes are performed subsequent to an ion implantation process, it is preferable that a user can designate to which heat treatment process the diffusion model considering the influence or contribution of the dislocation loop is used. However, there is no published literature which teaches this concept.